The present invention relates to semiconductor chip assemblies, and more particularly relates to semiconductor chip assemblies in which a plurality of chips are stacked one atop the other.
Semiconductor chips are commonly provided as individual, prepackaged units. Thus, the semiconductor chip itself typically is mounted to a substrate or chip carrier, which in turn is mounted on a circuit panel such as a printed circuit board. Considerable effort has been devoted towards development of so-called "multichip modules" in which several chips having related functions are attached to a common circuit panel and protected by a common package. This approach conserves some of the space which is ordinarily wasted by individual chip packages. However, most multichip module designs utilize a single layer of chips positioned side by side on a surface of a planar circuit panel. A typical chip is in the form of a flat, rectangular body with a large front face having contacts for connection to the internal circuitry of the chip. Each chip is mounted on the circuit panel with the front face or the rear face facing towards the panel. The so-called "flip chip" arrangement, in which the front face of the chip confronts the face of the circuit panel and the contacts on the chip are bonded to the circuit panel by solder balls or other interconnections provides a relatively compact arrangement; each chip occupies an area of the circuit panel equal to or slightly larger than the area of the chip front face. As disclosed, for example, in U.S. Pat. Nos. 5,148,265 and 5,148,266, assigned to the present assignee as the present application, certain innovative mounting techniques offer compactness approaching or equaling that of conventional flip chip bonding without the reliability and testing problems commonly encountered in that approach. When other mounting arrangements, such as tape automated bonding (TAB) or wire bonding are used, the area of the circuit panel required to mount each chip is substantially larger than the area of the chip front face. However, when only a single layer of chips is mounted on a circuit panel, using any of these approaches, the circuit panel has an area at least equal to the aggregate areas of the individual chips. This implies that the leads interconnecting the various chips in the assembly have substantial length. This in turn implies appreciable delay in transmission of signals between chips and hence limits the speed of operation of the assembly.
Various proposals have been advanced for packaging chips in a "stacked" arrangement one atop the other, in front face to rear face orientation. For example, certain embodiments of the invention disclosed in commonly assigned U.S. Pat. No. 5,347,159 allow stacking of chips one atop the other. Also, Kishida, U.S. Pat. No. 4,941,033 discloses an arrangement in which chips are stacked one atop the other and interconnected with one another by conductors on so-called "wiring films" associated with the chips. However, still further improvements in stacked chip assemblies and in components useful for making the same would be desirable. In particular, there are needs for chip assemblies which can be assembled readily using available techniques. There are further needs for such chip assemblies which can provide electrical conductive pathways connecting the chips to one another and to external circuit elements with low impedance and short circuit path lengths.
The stacked chip assemblies should deal effectively with the problems associated with heat generation in stacked chips. Chips dissipate electrical power as heat during operation. Where chips are stacked one atop the other, it is difficult to dissipate the heat generated by the chips in the middle of the stack. Consequently, the chips in such a stack may undergo substantial thermal expansion when operated and substantial contraction when operation ceases. This, in turn, imposes significant mechanical stress on the interconnecting arrangements and on the mountings which physically retain the chips. Stacked chip assemblies should be capable of withstanding thermal expansion and a contraction of the chips. Moreover, there has been a need for chip assemblies which provide enhanced heat dissipation, particularly from chips in the middle of a stack.